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Instruction set architecture
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991	PDF Document Add to Reading List Source URL: ece.uwaterloo.ca Language: English - Date: 2012-10-29 09:11:52 ARM architecture MOV MMIX PDP-11 architecture Computer architecture Instruction set architectures Instruction set
992	Ever Growing CPU States: Context Switch with Less Memory and Better Performance Fenghua Yu 1 Add to Reading List Source URL: events.linuxfoundation.org Language: English - Date: 2014-08-20 23:33:39 Process Central processing unit Instruction set architectures Streaming SIMD Extensions X86 Context switch Advanced Vector Extensions Processor register SIMD Computer architecture Computing X86 instructions
993	CHERI: A RISC capability machine for practical memory safety Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-08 10:34:26 Instruction set architectures Software engineering MIPS architecture Pointer Memory protection 64-bit Ring Capability-based addressing C Computer architecture Computing Memory management
994	C500 Microcontroller Family Architecture and Instruction Set UserÕs Manual 04.98 Add to Reading List Source URL: www.rigelcorp.com Language: English - Date: 2006-07-13 13:28:57 Computer architecture Intel MCS-51 Special function register Memory address Harvard architecture Addressing mode Memory-mapped I/O Atmel AVR Microcontrollers Computer hardware Computing
995	READS166 Users Guide Version 3.1x February[removed]RIGEL CORPORATION Add to Reading List Source URL: www.rigelcorp.com Language: English - Date: 2006-07-13 13:58:07 Computer engineering Rigel Addressing mode Instruction set Computer IBM Basic assembly language Assembly languages Computer architecture Computing
996	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-06-18 09:34:49 Ring MIPS architecture Instruction set 64-bit Hypervisor Reduced instruction set computing Kernel Capability-based security Memory protection Computer architecture Central processing unit Instruction set architectures
997	Bluespec Extensible RISC Implementation: BERI Hardware reference Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-14 10:37:05 MIPS architecture Instruction set Hardware description language R4000 64-bit Reduced instruction set computing Computer architecture Instruction set architectures Bluespec Inc.
998	Philips Semiconductors 80C51 family programmer’s guide and instruction set 80C51 Family Add to Reading List Source URL: www.rigelcorp.com Language: English - Date: 2006-07-13 13:19:20 X86 instructions Integrated circuits Intel MCS-51 Addressing mode INT TI MSP430 High Precision Event Timer Computer architecture Interrupts Microcontrollers
999	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-14 10:03:30 MIPS architecture Ring Instruction set 64-bit Hypervisor Reduced instruction set computing Capability-based security Kernel Memory protection Computer architecture Central processing unit Instruction set architectures
1000	Figure01_4_basic_functions Add to Reading List Source URL: www.altera.com Language: English ARM architecture Instruction set architectures Digital signal processing Interrupts Central processing unit Interrupt latency Nios II Interrupt handler Multi-core processor Computer architecture Computing Computer engineering